The present disclosure relates to semiconductor devices and, more particularly, to generating a bit line pre-charge voltage. Dynamic random access memory (DRAM) operates in a method of writing data by charges stored in a cell capacitor of a memory cell. Memory cells are connected to a bit line and a complementary bit line. When a read operation or a refresh operation is performed by the DRAM, a bit line sense amplifier senses and amplifies a voltage difference between the bit line and the complementary bit line. In order to sense data output to the bit line, the bit line is previously pre-charged by a bit line pre-charge voltage. In a case in which the bit line pre-charge voltage is unstable, when the data stored in the cell capacitor is sensed, a sensing margin may be reduced. Due to the sensing margin reduced by the unstable bit line pre-charge voltage, a sensing error of the bit line sensing amplifier occurs and the performance of the DRAM may deteriorate.